View MC100ES6039_281106.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Freescale Semiconductor Technical Data
MC100ES6039 Rev 2, 06/2005
3.3 V ECL/PECL/HSTL/LVDS /2/4, /4/6 Clock Generation Chip
The MC100ES6039 is a low skew /2/4, /4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple ES6039s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one ES6039, the MR pin need not be exercised as the internal divider design ensures synchronization between the /2/4 and the /4/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100ES Series contains temperature compensation. Features * * * * * * * * * * Maximum Frequency >1.0 GHz Typical 50 ps Output-to-Output Skew PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE = -3.135 V to -3.8 V Open Input Default State Synchronous Enable/Disable Master Reset for Synchronization of Multiple Chips VBB Output LVDS and HSTL Input Compatible 20-Lead Pb-Free Package Available
MC100ES6039
DW SUFFIX 20-LEAD SOIC PACKAGE CASE 751D-07
EG SUFFIX 20-LEAD TSSOP PACKAGE Pb-FREE PACKAGE CASE 751D-07
ORDERING INFORMATION
Device MC100ES6039DW MC100ES6039DWR2 MC100ES6039EG MC100ES6039EGR2 Package SO-20 SO-20 SO-20 (Pb-Free) SO-20 (Pb-Free)
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
VCC 20
Q0 19
Q0 18
Q1 17
Q1 16
Q2 15
Q2 14
Q3 13
Q3 12
VEE 11
Table 1. Pin Description
Pin CLK(1), EN(1) MR(1) CLK(1) Function ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff /2/4 Outputs ECL Diff /4/6 Outputs ECL Freq. Select Input /2/4 ECL Freq. Select Input /4/6 ECL Positive Supply ECL Negative Supply No Connect
1 VCC
2 EN
3 DIVSELb
4 CLK
5 CLK
6 VBB
7 MR
8 VCC
9 NC
10 DIVSELa
VBB Q0, Q1, Q0, Q1 Q2, Q3, Q2, Q3 DIVSELa(1) DIVSELb(1) VCC VEE NC
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View)
1. Pins will default low when left open. DIVSELa CLK CLK Q0 /2/4 R Q0 Q1 Q1 Q2 /4/6 R MR DIVSELb Q2 Q3 Q3
EN
VEE
Figure 2. Logic Diagram Table 2. Function Tables
CLK Z ZZ X X = Don't Care Z = Low-to-High Transition ZZ = High-to-Low Transition DIVSELa L H DIVSELb L H Q0:1 Outputs Divide by 2 Divide by 4 Q2:3 Outputs Divide by 4 Divide by 6 EN L H X MR L L H Function Divide Hold Q0:3 Reset Q0:3
MC100ES6039 2 Advanced Clock Drivers Device Data Freescale Semiconductor
CLK Q (/2) Q (/4) Q (/6)
Figure 3. Timing Diagram
CLK tRR RESET
Q (/n)
Figure 4. Timing Diagram Table 3. Attributes
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 k 75 k > 4 kV > 200 V > 2 kV
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
MC100ES6039 Advanced Clock Drivers Device Data Freescale Semiconductor 3
Table 4. Maximum Ratings(1)
Symbol VCC VEE VI Iout IBB TA Tstg JA Parameter PECL Mode Power Supply ECL Mode Power Supply PECL Mode Input Voltage ECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) 0 LFPM 500 LFPM 20 SOIC 20 SOIC Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 3.9 -3.9 3.9 -3.9 50 100 0.5 -40 to +85 -65 to +150 TBD TBD Units V V V V mA mA mA C C C/W C/W
1. Maximum Ratings are those values beyond which device damage may occur.
Table 5. DC Characteristics (VCC = 0 V, VEE = -3.8 V to -3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)(1)
Symbol IEE VOH VOL VIH VIL VBB VPP VCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage Output LOW Voltage
(2) (2)
-40C Min Typ 35 Max 60 Min
0C to 85C Typ 35 Max 60 VCC -750 VCC -880 VCC -1475 VCC -1200 1.4 VCC-0.7 150 0.5
Unit mA mV mV mV mV mV V V A A
VCC -1150 VCC -1020 VCC -800 VCC -1200 VCC -970 VCC -1165 VCC -1810 VCC -1400 0.12
(4)
VCC -1950 VCC -1620 VCC -1250 VCC -2000 VCC -1680 VCC -1300 VCC -880 VCC -1165 VCC -1475 VCC -1810 VCC -1200 VCC -1400 1.4 VCC-0.7 150 0.5 0.12 VEE+0.2
Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Reference Voltage Differential Input Voltage
(3)
Differential Cross Point Voltage Input HIGH Current Input LOW Current
VEE+0.2
1. MC100ES6139 circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 2. All loading with 50 to VCC-2.0 volts. 3. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 4. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification.
MC100ES6039 4 Advanced Clock Drivers Device Data Freescale Semiconductor
Table 6. AC Characteristics (VCC = 0 V, VEE = -3.8 V to -3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)(1)
Symbol fmax tPLH, tPHL tRR ts th tPW tSKEW Characteristic Maximum Frequency Propagation Delay Reset Recovery Setup Time Hold Time EN, CLK DIVSEL, CLK CLK, EN CLK, DIVSEL MR CLK, Q (Diff) MR, Q 575 500 200 200 400 100 200 550 100 120 180 50 140 450 80 50 300 1 150 VEE+0.2 50 1400 150 -40C Min Typ >1 875 850 575 500 200 200 400 100 200 550 100 120 180 50 140 450 80 50 300 1 1400 150 Max Min 25C Typ >1 875 850 575 500 200 200 400 100 200 550 100 120 180 50 140 450 80 50 300 1 1400 VCC-1.1 300 Max Min 85C Typ >1 875 850 Max Unit GHz ps ps ps ps ps ps ps ps ps ps ps ps mV V ps
Minimum Pulse Width
Within Device Skew Q, Q Q, Q @ Same Frequency Device-to-Device Skew(2) (RMS 1)
tJITTER Cycle-to-Cycle Jitter VPP VCMR tr tf
Input Voltage Swing (Differential) Differential Cross Point Voltage Output Rise/Fall Times (20% - 80%) Q, Q
VCC-1.1 VEE+0.2 300 50
VCC-1.1 VEE+0.2 300 50
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC -2.0 V. 2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs.
Q Driver Device Q 50 50
D Receiver Device D
VTT VTT = VCC -- 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation
MC100ES6039 Advanced Clock Drivers Device Data Freescale Semiconductor 5
PACKAGE DIMENSIONS
PAGE 1 OF 2
CASE 751D-07 ISSUE J 20-LEAD SOIC PACKAGE
MC100ES6039 6 Advanced Clock Drivers Device Data Freescale Semiconductor
PACKAGE DIMENSIONS
PAGE 2 OF 2
CASE 751D-07 ISSUE J 20-LEAD SOIC PACKAGE
MC100ES6039 Advanced Clock Drivers Device Data Freescale Semiconductor 7
How to Reach Us:
Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2005. All rights reserved.
MC100ES6039 Rev. 2 06/2005

▲Up To Search▲

Price & Availability of MC100ES6039

	To Download MC100ES6039 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .